In recent years, mobile phones and PDAs (digital personal assistants) and other mobile terminals have been spreading remarkably. One reason of the factors behind the rapid spread of these mobile terminals is the mount of the liquid crystal display devices thereon as output display parts. This is because liquid crystal display devices are display devices having the feature of basically not requiring power for driving and consuming low power.
In active matrix type display devices using polysilicon TFTs (thin film transistors) as switching elements for pixels, the trend is to integrally form a digital interface drive circuit with a display area where pixels are arranged in a matrix, on the same substrate.
In this integral drive circuit type display device, a horizontal drive system and a vertical drive system are arranged at a periphery (frame) in an effective display portion, these drive systems are integrally formed with the pixel area on the same substrate, using low temperature polysilicon TFTs.
FIG. 1 is a diagram showing the schematic configuration of a general integral drive circuit type display device (refer, for example, Patent Document 1).
In this liquid crystal display device, as shown in FIG. 1, an effective display portion 2 in which a plurality of pixels including liquid crystal cells are arranged in the matrix on a transparent insulating substrate, for example, a glass substrate 1, on which, a pair of horizontal drive circuits (H drivers) 3U and 3D arranged above and below the effective display portion 2 in FIG. 1, a vertical drive circuit (V driver) 4 arranged at a side of the effective display portion 2 in FIG. 1, one reference voltage generation circuit (REF DRV) 5 generating a plurality of reference voltages, a data processing circuit (DATAPRC) 6, etc. are integrated.
In this way, in the integral drive circuit type display device in FIG. 1, two horizontal drive circuits 3U and 3D are arranged on the two sides (above and below in FIG. 1) of the effective pixel portion 2, since data lines are separated into odd number lines and even number lines, and both lines are separately driven.
FIG. 2 is a block diagram showing an example of the configuration of the horizontal drive circuits 3U and 3D in FIG. 1 for separately driving odd number lines and even number lines.
As shown in FIG. 2, the horizontal drive circuit 3U for driving odd number lines and the horizontal drive circuit 3D for driving even number lines have the same configuration.
Specifically, they have shift register (HSR) groups 3HSRU and 3HSRD consecutively outputting shift pulses (sampling pulses) in synchronization with horizontal transfer clocks HCK (not shown), sampling latch circuit groups 3SMPLU and 3SMPLD consecutively sampling and latching digital image data by sampling pulses given from shift registers 31U and 31D, linear consecutive latch circuit groups 3LTCU and 3LTCD for linearly consecutive latch data of sampling latch circuits 32U and 32D, and digital/analog conversion circuit (DAC) groups 3DACU and 3DACD converting digital image data linearly sequenced at linearly sequencing latch circuits 33U and 33D to analog image signals
Note that usually level shift circuits are arranged at the input stages of the DACs 34U and 34D, and the data after being raised in level are input to the DAC 34.
Patent Document 1: Japanese Patent Publication (A) No. 2002-175033